Since the invention of the first transistor and after decades of rapid development, lateral and longitudinal dimensions of transistors have shrunk drastically. According to the forecast of International Technology Roadmap for Semiconductors (ITRS), the feature sizes of transistors may reach 7 nm by 2018. The continual reduction in the feature sizes results in continual enhancement of the performance (speed) of transistors. It also enables us to integrate more and more devices on a chip of the same area, and to make integrated circuits with better and better performance, while at the same time reducing unit function costs.
The continued shrinking in device feature sizes, however, also brings a series of challenges. When device feature sizes enter deep sub-micron range, short channel effect (SCE), drain induced barrier lower effect (DIBL), and hot carrier effect (HCE) etc., in the devices become more and more serious, degrading device performance. Conventional technologies mainly use channel engineering to solve these problems. Channel engineering attempts to enhance device performance by using non-uniform channel doping, so as to achieve continuous distribution of channel electric field.
In channel engineering, many devices with new channel architectures have been proposed, such as lightly doped drain (LDD), pocket and halo architectures, etc. The LDD architecture can effectively absorb the electric flux line on the drain side, reduce the device electric field on the drain side, and suppress hot carrier effect. By localized heavy doping on the source side, pocket and halo architecture can raise the potential barrier on the source side, weaken the effect of the drain side electric field on the potential barrier on the source side, effectively suppress the shifting of the device threshold voltage, source-drain punch through and device DIBL effect.
However, the LDD architecture discussed above can increase the device source-drain serial resistance, and reduce the device drive current. In the pocket architecture, the device threshold voltage may increase when the implant dosage/energy for the pockets increases, causing reduction of the saturated drive current, and reducing the device operation speed.
To solve the above problems, asymmetric gate field effect transistors are currently proposed. The so called asymmetric gate field effect transistor refers to a transistor in which the gate structure is different at the source region from that at the drain region, causing asymmetry in the electrical and physical properties at the carrier emitting side (source) and the carrier collecting side (drain), so that the overall performance of the transistor is more optimized. This is especially important in the design and optimization of future very small-scale transistors.
In conventional method of making asymmetric gate field effect transistors, a gate oxide layer having different thicknesses on the source side and the drain side is typically formed. By adjusting the gate oxide thickness on the source side and on the drain side, channel electric field distribution can be adjusted, and the overall performance of the transistors is enhanced.
However, the above method of making asymmetric gate field effect transistors by forming a gate oxide layer with uneven thicknesses on the source side and the drain side has certain difficulties in processing technologies, which are difficult to control in practice.